1. Field of the Invention
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to device structures, such as contact levels and metallization layers.
2. Description of the Related Art
Semiconductor devices are typically formed on substantially disc-shaped substrates made of any appropriate material. The majority of semiconductor devices including highly complex electronic circuits are currently being, and in the foreseeable future will be, manufactured on the basis of silicon, thereby rendering silicon substrates and silicon-containing substrates, such as silicon-on-insulator (SOI) substrates, viable carriers for forming semiconductor devices, such as microprocessors, SRAMs, ASICs (application specific ICs) and the like. The individual integrated circuits are arranged in an array form, wherein most of the manufacturing steps, which may add up to 500-1000 and more individual process steps in sophisticated integrated circuits, are performed simultaneously for all chip areas on the substrate, except for photolithography processes, certain metrology processes and packaging of the individual devices after dicing the substrate. Thus, economic constraints drive semiconductor manufacturers to steadily increase the substrate dimensions, thereby also increasing the area available for producing actual semiconductor devices.
In addition to increasing the substrate area, it is also important to optimize the utilization of the substrate area for a given substrate size so as to actually use as much substrate area as possible for semiconductor devices and/or test structures that may be used for process control. In an attempt to maximize the useful surface area for a given substrate size, the peripheral die regions are positioned as closely to the substrate perimeter as it is compatible with substrate handling processes. Generally, most of the manufacturing processes are performed in an automated manner, wherein the substrate handling is performed at the back side of the substrate and/or the substrate edge, which typically includes a bevel, at least at the front side of the substrate.
Due to the ongoing demand for shrinking the feature sizes of sophisticated semiconductor devices, highly complex and sensitive material layer systems may be increasingly used during the formation of the semiconductor devices. For example, copper and alloys thereof, in combination with low-k dielectric materials and ultra low-k dielectric materials, i.e., dielectric materials having a dielectric constant of approximately 3.0 and significantly less, have become a frequently used alternative for the formation of metallization layers which include metal lines and vias connecting to individual circuit elements by means of a corresponding contact level, which may also be comprised of complex interlayer dielectric materials in combination with contact elements. Although copper exhibits significant advantages compared to aluminum, i.e., a typical metallization material for metal systems of less complex structure, a plurality of challenges is also associated with the employment of copper and complex interlayer dielectric materials. For instance, copper may readily diffuse in silicon, silicon dioxide and a plurality of low-k dielectric materials, which may represent a challenge due to the fact that copper may significantly modify the electrical characteristics of silicon and thus the behavior of circuit elements, such as transistors and the like, even when being present in very small amounts. It is, therefore, essential to confine the copper material to the metal lines and vias by using appropriate insulating and conductive barrier materials that may strongly suppress the diffusion of copper into sensitive device areas and may also reduce the diffusion of reactive components, such as oxygen, fluorine and the like, into the copper metal regions. In addition, a contamination of process tools, such as transport systems, transport containers, robot handlers, wafer chucks and the like, must be effectively restricted since even minute amounts of copper deposited on the back side of a substrate may lead to diffusion of the copper into sensitive device areas. Moreover, due to the employment of low-k dielectric materials in combination with copper, additional problems may have to be dealt with owing to the reduced mechanical stability of the low-k dielectrics. Since at least some of the deposition processes used in fabricating semiconductor devices may not be efficiently restricted to the “active” substrate area, a stack of layers or material residues may also be formed at the substrate edge region including the bevel, thereby generating a mechanically unstable layer stack owing to process non-uniformities at the substrate edge, especially at the bevel of the substrate. Consequently, during the processing of the semiconductor substrates and the handling thereof, an increasing probability of generating any delaminations or flakes may be caused, wherein these material contaminants may be deposited in the central region of the substrate and/or on the back side of substrates and any substrate handling tools, thereby contributing to the contamination of further semiconductor substrates. Hence, although the employment of semiconductor substrates of increased diameter may generally result in an increased overall throughput, the contamination of the substrates in a very late manufacturing stage, i.e., after completing the basic configuration of circuit elements, such as transistors, may nevertheless result in a significant yield loss caused by the insufficient adhesion of complex material systems in the edge region of the semiconductor substrates.
In view of this situation, enhanced process techniques have been developed in which the edge region of the semiconductor substrates may be subjected to dedicated cleaning recipes, for instance on the basis of wet chemical chemistries or plasma assisted atmospheres, where the edge region may be selectively treated while substantially avoiding exposure of the central region, including circuit elements, to the corresponding cleaning processes. For instance, when forming circuit elements, such as transistors and the like, in and above a silicon-containing semiconductor layer, many of the deposition processes required during the complex manufacturing sequence may be substantially restricted to the central region of the semiconductor layer and intermittent spatially selective cleaning processes may be performed, thereby maintaining a substantially unmodified semiconductor surface, which may thus provide superior process conditions with respect to a contamination of the central substrate region comprising the circuit elements in a more or less pronounced manufacturing stage. It appears, however, that upon completing the basic circuit configuration, i.e., after forming a contact structure including interlayer dielectric materials and contact elements, a reduced degree of material adhesion may be observed in the edge region, in particular when complex interlayer dielectric materials in the form of low-k dielectrics may be increasingly deposited since these materials may preferably deposit at the edge region. For this reason, the overall material thickness may increase in the further advance of the manufacturing process, while at the same time the reduced mechanical stability and the overall reduced adhesion may then result in an increasing degree of contamination due to the delamination of material flakes and the like.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.